Info: Starting: Create block symbol file (.bsf)
Info: ip-generate --project-directory=D:/project/de0_nano/DE0_Nano_QSYS_DEMO/ --output-directory=D:/project/de0_nano/DE0_Nano_QSYS_DEMO/DE0_Nano_SOPC/ --report-file=bsf:D:/project/de0_nano/DE0_Nano_QSYS_DEMO/DE0_Nano_SOPC.bsf --system-info=DEVICE_FAMILY="Cyclone IV E" --system-info=DEVICE=EP4CE22F17C6 --system-info=DEVICE_SPEEDGRADE=6 --component-file=D:/project/de0_nano/DE0_Nano_QSYS_DEMO/DE0_Nano_SOPC.qsys
Progress: Loading DE0_Nano_QSYS_DEMO/DE0_Nano_SOPC.qsys
Progress: Reading input file
Progress: Adding clk_50 [clock_source 13.0]
Progress: Parameterizing module clk_50
Progress: Adding timer [altera_avalon_timer 13.0.1.99.2]
Progress: Parameterizing module timer
Progress: Adding key [altera_avalon_pio 13.0.1.99.2]
Progress: Parameterizing module key
Progress: Adding sw [altera_avalon_pio 13.0.1.99.2]
Progress: Parameterizing module sw
Progress: Adding led [altera_avalon_pio 13.0.1.99.2]
Progress: Parameterizing module led
Progress: Adding i2c_scl [altera_avalon_pio 13.0.1.99.2]
Progress: Parameterizing module i2c_scl
Progress: Adding i2c_sda [altera_avalon_pio 13.0.1.99.2]
Progress: Parameterizing module i2c_sda
Progress: Adding sdram [altera_avalon_new_sdram_controller 13.0.1.99.2]
Progress: Parameterizing module sdram
Progress: Adding altpll_sys [altpll 13.0]
Progress: Parameterizing module altpll_sys
Progress: Adding g_sensor_int [altera_avalon_pio 13.0.1.99.2]
Progress: Parameterizing module g_sensor_int
Progress: Adding epcs [altera_avalon_epcs_flash_controller 13.0.1.99.2]
Progress: Parameterizing module epcs
Progress: Adding jtag_uart [altera_avalon_jtag_uart 13.0.1.99.2]
Progress: Parameterizing module jtag_uart
Progress: Adding adc_spi_read [TERASIC_ADC_READ 1.0]
Progress: Parameterizing module adc_spi_read
Progress: Adding gsensor_spi [TERASIC_SPI_3WIRE 1.0]
Progress: Parameterizing module gsensor_spi
Progress: Adding select_i2c_clk [altera_avalon_pio 13.0.1.99.2]
Progress: Parameterizing module select_i2c_clk
Progress: Adding clock_crossing_io [altera_avalon_mm_clock_crossing_bridge 13.0]
Progress: Parameterizing module clock_crossing_io
Progress: Adding clock_crossing_io2 [altera_avalon_mm_clock_crossing_bridge 13.0]
Progress: Parameterizing module clock_crossing_io2
Progress: Adding cpu [altera_nios2_qsys 13.0]
Progress: Parameterizing module cpu
Progress: Adding sysid [altera_avalon_sysid_qsys 13.0]
Progress: Parameterizing module sysid
Progress: Adding c0 [altera_clock_bridge 13.0]
Progress: Parameterizing module c0
Progress: Adding c2 [altera_clock_bridge 13.0]
Progress: Parameterizing module c2
Progress: Adding c4 [altera_clock_bridge 13.0]
Progress: Parameterizing module c4
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
Info: DE0_Nano_SOPC.key: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: DE0_Nano_SOPC.sw: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: DE0_Nano_SOPC.i2c_sda: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: DE0_Nano_SOPC.g_sensor_int: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: DE0_Nano_SOPC.epcs: Dedicated AS interface is not supported, signals are exported to top level design.
Info: DE0_Nano_SOPC.cpu: CPUID control register value is 0. Please manually assign CPUID if creating multiple Nios II system
Info: DE0_Nano_SOPC.sysid: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID
Info: DE0_Nano_SOPC.sysid: Time stamp will be automatically updated when this component is generated.
Info: ip-generate succeeded.
Info: Finished: Create block symbol file (.bsf)
Info: 
Info: Starting: Create HDL design files for synthesis
Info: ip-generate --project-directory=D:/project/de0_nano/DE0_Nano_QSYS_DEMO/ --output-directory=D:/project/de0_nano/DE0_Nano_QSYS_DEMO/DE0_Nano_SOPC/synthesis/ --file-set=QUARTUS_SYNTH --report-file=sopcinfo:D:/project/de0_nano/DE0_Nano_QSYS_DEMO/DE0_Nano_SOPC.sopcinfo --report-file=html:D:/project/de0_nano/DE0_Nano_QSYS_DEMO/DE0_Nano_SOPC.html --report-file=qip:D:/project/de0_nano/DE0_Nano_QSYS_DEMO/DE0_Nano_SOPC/synthesis/DE0_Nano_SOPC.qip --report-file=cmp:D:/project/de0_nano/DE0_Nano_QSYS_DEMO/DE0_Nano_SOPC.cmp --report-file=svd --system-info=DEVICE_FAMILY="Cyclone IV E" --system-info=DEVICE=EP4CE22F17C6 --system-info=DEVICE_SPEEDGRADE=6 --component-file=D:/project/de0_nano/DE0_Nano_QSYS_DEMO/DE0_Nano_SOPC.qsys --language=VERILOG
Progress: Loading DE0_Nano_QSYS_DEMO/DE0_Nano_SOPC.qsys
Progress: Reading input file
Progress: Adding clk_50 [clock_source 13.0]
Progress: Parameterizing module clk_50
Progress: Adding timer [altera_avalon_timer 13.0.1.99.2]
Progress: Parameterizing module timer
Progress: Adding key [altera_avalon_pio 13.0.1.99.2]
Progress: Parameterizing module key
Progress: Adding sw [altera_avalon_pio 13.0.1.99.2]
Progress: Parameterizing module sw
Progress: Adding led [altera_avalon_pio 13.0.1.99.2]
Progress: Parameterizing module led
Progress: Adding i2c_scl [altera_avalon_pio 13.0.1.99.2]
Progress: Parameterizing module i2c_scl
Progress: Adding i2c_sda [altera_avalon_pio 13.0.1.99.2]
Progress: Parameterizing module i2c_sda
Progress: Adding sdram [altera_avalon_new_sdram_controller 13.0.1.99.2]
Progress: Parameterizing module sdram
Progress: Adding altpll_sys [altpll 13.0]
Progress: Parameterizing module altpll_sys
Progress: Adding g_sensor_int [altera_avalon_pio 13.0.1.99.2]
Progress: Parameterizing module g_sensor_int
Progress: Adding epcs [altera_avalon_epcs_flash_controller 13.0.1.99.2]
Progress: Parameterizing module epcs
Progress: Adding jtag_uart [altera_avalon_jtag_uart 13.0.1.99.2]
Progress: Parameterizing module jtag_uart
Progress: Adding adc_spi_read [TERASIC_ADC_READ 1.0]
Progress: Parameterizing module adc_spi_read
Progress: Adding gsensor_spi [TERASIC_SPI_3WIRE 1.0]
Progress: Parameterizing module gsensor_spi
Progress: Adding select_i2c_clk [altera_avalon_pio 13.0.1.99.2]
Progress: Parameterizing module select_i2c_clk
Progress: Adding clock_crossing_io [altera_avalon_mm_clock_crossing_bridge 13.0]
Progress: Parameterizing module clock_crossing_io
Progress: Adding clock_crossing_io2 [altera_avalon_mm_clock_crossing_bridge 13.0]
Progress: Parameterizing module clock_crossing_io2
Progress: Adding cpu [altera_nios2_qsys 13.0]
Progress: Parameterizing module cpu
Progress: Adding sysid [altera_avalon_sysid_qsys 13.0]
Progress: Parameterizing module sysid
Progress: Adding c0 [altera_clock_bridge 13.0]
Progress: Parameterizing module c0
Progress: Adding c2 [altera_clock_bridge 13.0]
Progress: Parameterizing module c2
Progress: Adding c4 [altera_clock_bridge 13.0]
Progress: Parameterizing module c4
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
Info: DE0_Nano_SOPC.key: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: DE0_Nano_SOPC.sw: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: DE0_Nano_SOPC.i2c_sda: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: DE0_Nano_SOPC.g_sensor_int: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: DE0_Nano_SOPC.epcs: Dedicated AS interface is not supported, signals are exported to top level design.
Info: DE0_Nano_SOPC.cpu: CPUID control register value is 0. Please manually assign CPUID if creating multiple Nios II system
Info: DE0_Nano_SOPC.sysid: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID
Info: DE0_Nano_SOPC.sysid: Time stamp will be automatically updated when this component is generated.
Info: DE0_Nano_SOPC: Generating DE0_Nano_SOPC "DE0_Nano_SOPC" for QUARTUS_SYNTH
Info: pipeline_bridge_swap_transform: After transform: 22 modules, 89 connections
Info: No custom instruction connections, skipping transform 
Info: merlin_translator_transform: After transform: 44 modules, 177 connections
Info: merlin_domain_transform: After transform: 90 modules, 475 connections
Info: merlin_router_transform: After transform: 112 modules, 563 connections
Info: merlin_traffic_limiter_transform: After transform: 116 modules, 583 connections
Info: merlin_burst_transform: After transform: 117 modules, 587 connections
Info: reset_adaptation_transform: After transform: 121 modules, 465 connections
Info: merlin_network_to_switch_transform: After transform: 162 modules, 549 connections
Info: merlin_width_transform: After transform: 164 modules, 555 connections
Info: Inserting clock-crossing logic between cmd_xbar_demux_001.src2 and cmd_xbar_mux_002.sink0
Info: Inserting clock-crossing logic between cmd_xbar_demux_001.src4 and cmd_xbar_mux_004.sink0
Info: Inserting clock-crossing logic between rsp_xbar_demux_002.src0 and rsp_xbar_mux_001.sink2
Info: Inserting clock-crossing logic between rsp_xbar_demux_004.src0 and rsp_xbar_mux_001.sink4
Info: com_altera_sopcmodel_transforms_avalon_ClockCrossingTransform: After transform: 168 modules, 575 connections
Info: limiter_update_transform: After transform: 168 modules, 579 connections
Info: merlin_mm_transform: After transform: 168 modules, 579 connections
Info: merlin_interrupt_mapper_transform: After transform: 169 modules, 582 connections
Info: merlin_interrupt_sync_transform: After transform: 174 modules, 607 connections
Warning: DE0_Nano_SOPC: "No matching role found for epcs:epcs_control_port:endofpacket (endofpacket)"
Warning: DE0_Nano_SOPC: "No matching role found for epcs:epcs_control_port:dataavailable (dataavailable)"
Warning: DE0_Nano_SOPC: "No matching role found for epcs:epcs_control_port:readyfordata (readyfordata)"
Info: timer: Starting RTL generation for module 'DE0_Nano_SOPC_timer'
Info: timer:   Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer/generate_rtl.pl --name=DE0_Nano_SOPC_timer --dir=C:/Users/User/AppData/Local/Temp/alt5973_8829614849190838295.dir/0003_timer_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/User/AppData/Local/Temp/alt5973_8829614849190838295.dir/0003_timer_gen//DE0_Nano_SOPC_timer_component_configuration.pl  --do_build_sim=0  ]
Info: timer: Done RTL generation for module 'DE0_Nano_SOPC_timer'
Info: timer: "DE0_Nano_SOPC" instantiated altera_avalon_timer "timer"
Info: key: Starting RTL generation for module 'DE0_Nano_SOPC_key'
Info: key:   Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=DE0_Nano_SOPC_key --dir=C:/Users/User/AppData/Local/Temp/alt5973_8829614849190838295.dir/0004_key_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/User/AppData/Local/Temp/alt5973_8829614849190838295.dir/0004_key_gen//DE0_Nano_SOPC_key_component_configuration.pl  --do_build_sim=0  ]
Info: key: Done RTL generation for module 'DE0_Nano_SOPC_key'
Info: key: "DE0_Nano_SOPC" instantiated altera_avalon_pio "key"
Info: sw: Starting RTL generation for module 'DE0_Nano_SOPC_sw'
Info: sw:   Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=DE0_Nano_SOPC_sw --dir=C:/Users/User/AppData/Local/Temp/alt5973_8829614849190838295.dir/0005_sw_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/User/AppData/Local/Temp/alt5973_8829614849190838295.dir/0005_sw_gen//DE0_Nano_SOPC_sw_component_configuration.pl  --do_build_sim=0  ]
Info: sw: Done RTL generation for module 'DE0_Nano_SOPC_sw'
Info: sw: "DE0_Nano_SOPC" instantiated altera_avalon_pio "sw"
Info: led: Starting RTL generation for module 'DE0_Nano_SOPC_led'
Info: led:   Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=DE0_Nano_SOPC_led --dir=C:/Users/User/AppData/Local/Temp/alt5973_8829614849190838295.dir/0006_led_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/User/AppData/Local/Temp/alt5973_8829614849190838295.dir/0006_led_gen//DE0_Nano_SOPC_led_component_configuration.pl  --do_build_sim=0  ]
Info: led: Done RTL generation for module 'DE0_Nano_SOPC_led'
Info: led: "DE0_Nano_SOPC" instantiated altera_avalon_pio "led"
Info: i2c_scl: Starting RTL generation for module 'DE0_Nano_SOPC_i2c_scl'
Info: i2c_scl:   Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=DE0_Nano_SOPC_i2c_scl --dir=C:/Users/User/AppData/Local/Temp/alt5973_8829614849190838295.dir/0007_i2c_scl_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/User/AppData/Local/Temp/alt5973_8829614849190838295.dir/0007_i2c_scl_gen//DE0_Nano_SOPC_i2c_scl_component_configuration.pl  --do_build_sim=0  ]
Info: i2c_scl: Done RTL generation for module 'DE0_Nano_SOPC_i2c_scl'
Info: i2c_scl: "DE0_Nano_SOPC" instantiated altera_avalon_pio "i2c_scl"
Info: i2c_sda: Starting RTL generation for module 'DE0_Nano_SOPC_i2c_sda'
Info: i2c_sda:   Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=DE0_Nano_SOPC_i2c_sda --dir=C:/Users/User/AppData/Local/Temp/alt5973_8829614849190838295.dir/0008_i2c_sda_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/User/AppData/Local/Temp/alt5973_8829614849190838295.dir/0008_i2c_sda_gen//DE0_Nano_SOPC_i2c_sda_component_configuration.pl  --do_build_sim=0  ]
Info: i2c_sda: Done RTL generation for module 'DE0_Nano_SOPC_i2c_sda'
Info: i2c_sda: "DE0_Nano_SOPC" instantiated altera_avalon_pio "i2c_sda"
Info: sdram: Starting RTL generation for module 'DE0_Nano_SOPC_sdram'
Info: sdram:   Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_new_sdram_controller -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_new_sdram_controller/generate_rtl.pl --name=DE0_Nano_SOPC_sdram --dir=C:/Users/User/AppData/Local/Temp/alt5973_8829614849190838295.dir/0009_sdram_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/User/AppData/Local/Temp/alt5973_8829614849190838295.dir/0009_sdram_gen//DE0_Nano_SOPC_sdram_component_configuration.pl  --do_build_sim=0  ]
Info: sdram: Done RTL generation for module 'DE0_Nano_SOPC_sdram'
Info: sdram: "DE0_Nano_SOPC" instantiated altera_avalon_new_sdram_controller "sdram"
Info: altpll_sys: "DE0_Nano_SOPC" instantiated altpll "altpll_sys"
Info: g_sensor_int: Starting RTL generation for module 'DE0_Nano_SOPC_g_sensor_int'
Info: g_sensor_int:   Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=DE0_Nano_SOPC_g_sensor_int --dir=C:/Users/User/AppData/Local/Temp/alt5973_8829614849190838295.dir/0012_g_sensor_int_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/User/AppData/Local/Temp/alt5973_8829614849190838295.dir/0012_g_sensor_int_gen//DE0_Nano_SOPC_g_sensor_int_component_configuration.pl  --do_build_sim=0  ]
Info: g_sensor_int: Done RTL generation for module 'DE0_Nano_SOPC_g_sensor_int'
Info: g_sensor_int: "DE0_Nano_SOPC" instantiated altera_avalon_pio "g_sensor_int"
Info: epcs: Starting RTL generation for module 'DE0_Nano_SOPC_epcs'
Info: epcs:   Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_epcs_flash_controller -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_epcs_flash_controller/generate_rtl.pl --name=DE0_Nano_SOPC_epcs --dir=C:/Users/User/AppData/Local/Temp/alt5973_8829614849190838295.dir/0013_epcs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/User/AppData/Local/Temp/alt5973_8829614849190838295.dir/0013_epcs_gen//DE0_Nano_SOPC_epcs_component_configuration.pl  --do_build_sim=0  ]
Info: epcs: Done RTL generation for module 'DE0_Nano_SOPC_epcs'
Info: epcs: "DE0_Nano_SOPC" instantiated altera_avalon_epcs_flash_controller "epcs"
Info: jtag_uart: Starting RTL generation for module 'DE0_Nano_SOPC_jtag_uart'
Info: jtag_uart:   Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=DE0_Nano_SOPC_jtag_uart --dir=C:/Users/User/AppData/Local/Temp/alt5973_8829614849190838295.dir/0014_jtag_uart_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/User/AppData/Local/Temp/alt5973_8829614849190838295.dir/0014_jtag_uart_gen//DE0_Nano_SOPC_jtag_uart_component_configuration.pl  --do_build_sim=0  ]
Info: jtag_uart: Done RTL generation for module 'DE0_Nano_SOPC_jtag_uart'
Info: jtag_uart: "DE0_Nano_SOPC" instantiated altera_avalon_jtag_uart "jtag_uart"
Info: adc_spi_read: "DE0_Nano_SOPC" instantiated TERASIC_ADC_READ "adc_spi_read"
Info: gsensor_spi: "DE0_Nano_SOPC" instantiated TERASIC_SPI_3WIRE "gsensor_spi"
Info: select_i2c_clk: Starting RTL generation for module 'DE0_Nano_SOPC_select_i2c_clk'
Info: select_i2c_clk:   Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=DE0_Nano_SOPC_select_i2c_clk --dir=C:/Users/User/AppData/Local/Temp/alt5973_8829614849190838295.dir/0015_select_i2c_clk_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/User/AppData/Local/Temp/alt5973_8829614849190838295.dir/0015_select_i2c_clk_gen//DE0_Nano_SOPC_select_i2c_clk_component_configuration.pl  --do_build_sim=0  ]
Info: select_i2c_clk: Done RTL generation for module 'DE0_Nano_SOPC_select_i2c_clk'
Info: select_i2c_clk: "DE0_Nano_SOPC" instantiated altera_avalon_pio "select_i2c_clk"
Info: clock_crossing_io: "DE0_Nano_SOPC" instantiated altera_avalon_mm_clock_crossing_bridge "clock_crossing_io"
Info: cpu: Starting RTL generation for module 'DE0_Nano_SOPC_cpu'
Info: cpu:   Generation command is [exec C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/eperl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/cpu_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/nios_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -- C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/generate_rtl.epl --name=DE0_Nano_SOPC_cpu --dir=C:/Users/User/AppData/Local/Temp/alt5973_8829614849190838295.dir/0016_cpu_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/User/AppData/Local/Temp/alt5973_8829614849190838295.dir/0016_cpu_gen//DE0_Nano_SOPC_cpu_processor_configuration.pl  --do_build_sim=0    --bogus  ]
Info: cpu: # 2013.09.25 10:19:35 (*) Starting Nios II generation
Info: cpu: # 2013.09.25 10:19:35 (*)   Checking for plaintext license.
Info: cpu: # 2013.09.25 10:19:35 (*)   Plaintext license not found.
Info: cpu: # 2013.09.25 10:19:35 (*)   Checking for encrypted license (non-evaluation).
Info: cpu: # 2013.09.25 10:19:36 (*)   Encrypted license found.  SOF will not be time-limited.
Info: cpu: # 2013.09.25 10:19:36 (*)   Elaborating CPU configuration settings
Info: cpu: # 2013.09.25 10:19:36 (*)   Creating all objects for CPU
Info: cpu: # 2013.09.25 10:19:36 (*)     Testbench
Info: cpu: # 2013.09.25 10:19:36 (*)     Instruction decoding
Info: cpu: # 2013.09.25 10:19:36 (*)       Instruction fields
Info: cpu: # 2013.09.25 10:19:36 (*)       Instruction decodes
Info: cpu: # 2013.09.25 10:19:36 (*)       Signals for RTL simulation waveforms
Info: cpu: # 2013.09.25 10:19:36 (*)       Instruction controls
Info: cpu: # 2013.09.25 10:19:36 (*)     Pipeline frontend
Info: cpu: # 2013.09.25 10:19:37 (*)     Pipeline backend
Info: cpu: # 2013.09.25 10:19:39 (*)   Generating RTL from CPU objects
Info: cpu: # 2013.09.25 10:19:42 (*)   Creating encrypted RTL
Info: cpu: # 2013.09.25 10:19:43 (*) Done Nios II generation
Info: cpu: Done RTL generation for module 'DE0_Nano_SOPC_cpu'
Info: cpu: "DE0_Nano_SOPC" instantiated altera_nios2_qsys "cpu"
Info: sysid: "DE0_Nano_SOPC" instantiated altera_avalon_sysid_qsys "sysid"
Info: cpu_instruction_master_translator: "DE0_Nano_SOPC" instantiated altera_merlin_master_translator "cpu_instruction_master_translator"
Info: cpu_jtag_debug_module_translator: "DE0_Nano_SOPC" instantiated altera_merlin_slave_translator "cpu_jtag_debug_module_translator"
Info: cpu_instruction_master_translator_avalon_universal_master_0_agent: "DE0_Nano_SOPC" instantiated altera_merlin_master_agent "cpu_instruction_master_translator_avalon_universal_master_0_agent"
Info: cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent: "DE0_Nano_SOPC" instantiated altera_merlin_slave_agent "cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent"
Info: cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo: "DE0_Nano_SOPC" instantiated altera_avalon_sc_fifo "cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo"
Info: addr_router: "DE0_Nano_SOPC" instantiated altera_merlin_router "addr_router"
Info: addr_router_001: "DE0_Nano_SOPC" instantiated altera_merlin_router "addr_router_001"
Info: id_router: "DE0_Nano_SOPC" instantiated altera_merlin_router "id_router"
Info: id_router_001: "DE0_Nano_SOPC" instantiated altera_merlin_router "id_router_001"
Info: id_router_002: "DE0_Nano_SOPC" instantiated altera_merlin_router "id_router_002"
Info: addr_router_002: "DE0_Nano_SOPC" instantiated altera_merlin_router "addr_router_002"
Info: id_router_007: "DE0_Nano_SOPC" instantiated altera_merlin_router "id_router_007"
Info: addr_router_003: "DE0_Nano_SOPC" instantiated altera_merlin_router "addr_router_003"
Info: id_router_014: "DE0_Nano_SOPC" instantiated altera_merlin_router "id_router_014"
Info: limiter: "DE0_Nano_SOPC" instantiated altera_merlin_traffic_limiter "limiter"
Info: burst_adapter: "DE0_Nano_SOPC" instantiated altera_merlin_burst_adapter "burst_adapter"
Info: rst_controller: "DE0_Nano_SOPC" instantiated altera_reset_controller "rst_controller"
Info: cmd_xbar_demux: "DE0_Nano_SOPC" instantiated altera_merlin_demultiplexer "cmd_xbar_demux"
Info: cmd_xbar_demux_001: "DE0_Nano_SOPC" instantiated altera_merlin_demultiplexer "cmd_xbar_demux_001"
Info: cmd_xbar_mux: "DE0_Nano_SOPC" instantiated altera_merlin_multiplexer "cmd_xbar_mux"
Info: rsp_xbar_demux: "DE0_Nano_SOPC" instantiated altera_merlin_demultiplexer "rsp_xbar_demux"
Info: rsp_xbar_demux_002: "DE0_Nano_SOPC" instantiated altera_merlin_demultiplexer "rsp_xbar_demux_002"
Info: rsp_xbar_mux: "DE0_Nano_SOPC" instantiated altera_merlin_multiplexer "rsp_xbar_mux"
Info: Reusing file D:/project/de0_nano/DE0_Nano_QSYS_DEMO/DE0_Nano_SOPC/synthesis/submodules/altera_merlin_arbitrator.sv
Info: rsp_xbar_mux_001: "DE0_Nano_SOPC" instantiated altera_merlin_multiplexer "rsp_xbar_mux_001"
Info: Reusing file D:/project/de0_nano/DE0_Nano_QSYS_DEMO/DE0_Nano_SOPC/synthesis/submodules/altera_merlin_arbitrator.sv
Info: cmd_xbar_demux_002: "DE0_Nano_SOPC" instantiated altera_merlin_demultiplexer "cmd_xbar_demux_002"
Info: rsp_xbar_demux_007: "DE0_Nano_SOPC" instantiated altera_merlin_demultiplexer "rsp_xbar_demux_007"
Info: rsp_xbar_mux_002: "DE0_Nano_SOPC" instantiated altera_merlin_multiplexer "rsp_xbar_mux_002"
Info: Reusing file D:/project/de0_nano/DE0_Nano_QSYS_DEMO/DE0_Nano_SOPC/synthesis/submodules/altera_merlin_arbitrator.sv
Info: cmd_xbar_demux_003: "DE0_Nano_SOPC" instantiated altera_merlin_demultiplexer "cmd_xbar_demux_003"
Info: rsp_xbar_demux_014: "DE0_Nano_SOPC" instantiated altera_merlin_demultiplexer "rsp_xbar_demux_014"
Info: rsp_xbar_mux_003: "DE0_Nano_SOPC" instantiated altera_merlin_multiplexer "rsp_xbar_mux_003"
Info: Reusing file D:/project/de0_nano/DE0_Nano_QSYS_DEMO/DE0_Nano_SOPC/synthesis/submodules/altera_merlin_arbitrator.sv
Info: width_adapter: "DE0_Nano_SOPC" instantiated altera_merlin_width_adapter "width_adapter"
Info: Reusing file D:/project/de0_nano/DE0_Nano_QSYS_DEMO/DE0_Nano_SOPC/synthesis/submodules/altera_merlin_address_alignment.sv
Info: Reusing file D:/project/de0_nano/DE0_Nano_QSYS_DEMO/DE0_Nano_SOPC/synthesis/submodules/altera_merlin_burst_uncompressor.sv
Info: crosser: "DE0_Nano_SOPC" instantiated altera_avalon_st_handshake_clock_crosser "crosser"
Info: Reusing file D:/project/de0_nano/DE0_Nano_QSYS_DEMO/DE0_Nano_SOPC/synthesis/submodules/altera_avalon_st_pipeline_base.v
Info: irq_mapper: "DE0_Nano_SOPC" instantiated altera_irq_mapper "irq_mapper"
Info: irq_synchronizer: "DE0_Nano_SOPC" instantiated altera_irq_clock_crosser "irq_synchronizer"
Info: DE0_Nano_SOPC: Done DE0_Nano_SOPC" with 52 modules, 220 files, 4152194 bytes
Info: ip-generate succeeded.
Info: Finished: Create HDL design files for synthesis
