---

clk_50

clock_source v10.1

Parameters clockFrequency 50000000 clockFrequencyKnown true inputClockFrequency 0 resetSynchronousEdges NONE deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

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cpu

altera_nios2 v10.1

Parameters userDefinedSettings tightlyCoupledInstructionMaster3MapParam tightlyCoupledInstructionMaster3AddrWidth 1 tightlyCoupledInstructionMaster2MapParam tightlyCoupledInstructionMaster2AddrWidth 1 tightlyCoupledInstructionMaster1MapParam tightlyCoupledInstructionMaster1AddrWidth 1 tightlyCoupledInstructionMaster0MapParam tightlyCoupledInstructionMaster0AddrWidth 1 tightlyCoupledDataMaster3MapParam tightlyCoupledDataMaster3AddrWidth 1 tightlyCoupledDataMaster2MapParam tightlyCoupledDataMaster2AddrWidth 1 tightlyCoupledDataMaster1MapParam tightlyCoupledDataMaster1AddrWidth 1 tightlyCoupledDataMaster0MapParam tightlyCoupledDataMaster0AddrWidth 1 setting_showUnpublishedSettings false setting_showInternalSettings false setting_shadowRegisterSets 0 setting_preciseSlaveAccessErrorException false setting_preciseIllegalMemAccessException false setting_preciseDivisionErrorException false setting_performanceCounter false setting_perfCounterWidth _32 setting_interruptControllerType Internal setting_illegalMemAccessDetection false setting_illegalInstructionsTrap false setting_fullWaveformSignals false setting_extraExceptionInfo false setting_exportPCB false setting_debugSimGen false setting_clearXBitsLDNonBypass true setting_branchPredictionType Automatic setting_bit31BypassDCache true setting_bigEndian false setting_bhtPtrSz _8 setting_bhtIndexPcOnly false setting_avalonDebugPortPresent false setting_alwaysEncrypt true setting_allowFullAddressRange false setting_activateTrace true setting_activateTestEndChecker false setting_activateMonitors true setting_activateModelChecker false setting_HDLSimCachesCleared true setting_HBreakTest false resetSlave sdram.s1 resetOffset 0 muldiv_multiplierType EmbeddedMulFast muldiv_divider false mpu_useLimit false mpu_numOfInstRegion 8 mpu_numOfDataRegion 8 mpu_minInstRegionSize _12 mpu_minDataRegionSize _12 mpu_enabled false mmu_uitlbNumEntries _4 mmu_udtlbNumEntries _6 mmu_tlbPtrSz _7 mmu_tlbNumWays _16 mmu_processIDNumBits _8 mmu_enabled false mmu_autoAssignTlbPtrSz true mmu_TLBMissExcSlave mmu_TLBMissExcOffset 0 manuallyAssignCpuID false internalIrqMaskSystemInfo 63 instSlaveMapParam <address-map><slave name='sdram.s1' start='0x2000000' end='0x4000000' /><slave name='cpu.jtag_debug_module' start='0x6000800' end='0x6001000' /></address-map> instAddrWidth 27 impl Fast icache_size _1024 icache_ramBlockType Automatic icache_numTCIM _0 icache_burstType None exceptionSlave sdram.s1 exceptionOffset 32 deviceFeaturesSystemInfo M512_MEMORY 0 M4K_MEMORY 0 M9K_MEMORY 1 M20K_MEMORY 0 M144K_MEMORY 0 MRAM_MEMORY 0 MLAB_MEMORY 0 ESB 0 EPCS 1 DSP 0 EMUL 1 HARDCOPY 0 LVDS_IO 1 ADDRESS_STALL 1 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 DSP_SHIFTER_BLOCK 0 deviceFamilyName Cyclone IV E debug_triggerArming true debug_level Level1 debug_jtagInstanceID 0 debug_embeddedPLL true debug_debugReqSignals false debug_assignJtagInstanceID false debug_OCIOnchipTrace _128 dcache_size _512 dcache_ramBlockType Automatic dcache_omitDataMaster false dcache_numTCDM _0 dcache_lineSize _32 dcache_bursts false dataSlaveMapParam <address-map><slave name='sdram.s1' start='0x2000000' end='0x4000000' /><slave name='timer.s1' start='0x4000000' end='0x4000020' /><slave name='key.s1' start='0x4000020' end='0x4000030' /><slave name='led.s1' start='0x4000030' end='0x4000040' /><slave name='sw.s1' start='0x4000040' end='0x4000050' /><slave name='g_sensor_int.s1' start='0x4000050' end='0x4000060' /><slave name='select_i2c_clk.s1' start='0x4000060' end='0x4000070' /><slave name='sysid.control_slave' start='0x4000070' end='0x4000078' /><slave name='epcs.epcs_control_port' start='0x5000000' end='0x5000800' /><slave name='gsensor_spi.slave' start='0x5000800' end='0x5000840' /><slave name='i2c_sda.s1' start='0x5000840' end='0x5000850' /><slave name='i2c_scl.s1' start='0x5000850' end='0x5000860' /><slave name='cpu.jtag_debug_module' start='0x6000800' end='0x6001000' /><slave name='altpll_sys.pll_slave' start='0x6001000' end='0x6001010' /><slave name='jtag_uart.avalon_jtag_slave' start='0x6001010' end='0x6001018' /><slave name='adc_spi_read.slave' start='0x6001018' end='0x600101C' /></address-map> dataAddrWidth 27 customInstSlavesSystemInfo <info/> cpuReset false cpuID 0 clockFrequency 100000000 breakSlave cpu.jtag_debug_module breakOffset 32 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments CPU_IMPLEMENTATION "fast" BIG_ENDIAN 0 CPU_FREQ 100000000u ICACHE_LINE_SIZE 32 ICACHE_LINE_SIZE_LOG2 5 ICACHE_SIZE 1024 DCACHE_LINE_SIZE 32 DCACHE_LINE_SIZE_LOG2 5 DCACHE_SIZE 512 INITDA_SUPPORTED FLUSHDA_SUPPORTED HAS_JMPI_INSTRUCTION EXCEPTION_ADDR 0x2000020 RESET_ADDR 0x2000000 BREAK_ADDR 0x6000820 HAS_DEBUG_STUB HAS_DEBUG_CORE 1 CPU_ID_SIZE 1 CPU_ID_VALUE 0x0 HARDWARE_DIVIDE_PRESENT 0 HARDWARE_MULTIPLY_PRESENT 1 HARDWARE_MULX_PRESENT 0 INST_ADDR_WIDTH 27 DATA_ADDR_WIDTH 27 NUM_OF_SHADOW_REG_SETS 0

---

sysid

altera_avalon_sysid v10.1

Parameters id 0 timestamp 1298277150 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments ID 0u TIMESTAMP 1298277150u

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timer

altera_avalon_timer v10.1

Parameters alwaysRun false counterSize 32 fixedPeriod false period 1 periodUnits MSEC resetOutput false snapshot true systemFrequency 10000000 timeoutPulseOutput false timerPreset CUSTOM deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments ALWAYS_RUN 0 FIXED_PERIOD 0 SNAPSHOT 1 PERIOD 1 PERIOD_UNITS "ms" RESET_OUTPUT 0 TIMEOUT_PULSE_OUTPUT 0 FREQ 10000000u LOAD_VALUE 9999ULL COUNTER_SIZE 32 MULT 0.0010 TICKS_PER_SEC 1000u

---

key

altera_avalon_pio v10.1

Parameters bitClearingEdgeCapReg false bitModifyingOutReg false captureEdge true clockRate 10000000 direction Input edgeType FALLING generateIRQ true irqType EDGE resetValue 0 simDoTestBenchWiring false simDrivenValue 0 width 2 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments DO_TEST_BENCH_WIRING 0 DRIVEN_SIM_VALUE 0x0 HAS_TRI 0 HAS_OUT 0 HAS_IN 1 CAPTURE 1 BIT_CLEARING_EDGE_REGISTER 0 BIT_MODIFYING_OUTPUT_REGISTER 0 DATA_WIDTH 2 RESET_VALUE 0x0 EDGE_TYPE "FALLING" IRQ_TYPE "EDGE" FREQ 10000000u

---

sw

altera_avalon_pio v10.1

Parameters bitClearingEdgeCapReg false bitModifyingOutReg false captureEdge true clockRate 10000000 direction Input edgeType ANY generateIRQ true irqType EDGE resetValue 0 simDoTestBenchWiring false simDrivenValue 0 width 4 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments DO_TEST_BENCH_WIRING 0 DRIVEN_SIM_VALUE 0x0 HAS_TRI 0 HAS_OUT 0 HAS_IN 1 CAPTURE 1 BIT_CLEARING_EDGE_REGISTER 0 BIT_MODIFYING_OUTPUT_REGISTER 0 DATA_WIDTH 4 RESET_VALUE 0x0 EDGE_TYPE "ANY" IRQ_TYPE "EDGE" FREQ 10000000u

---

led

altera_avalon_pio v10.1

Parameters bitClearingEdgeCapReg false bitModifyingOutReg false captureEdge false clockRate 10000000 direction Output edgeType RISING generateIRQ false irqType LEVEL resetValue 0 simDoTestBenchWiring false simDrivenValue 0 width 8 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments DO_TEST_BENCH_WIRING 0 DRIVEN_SIM_VALUE 0x0 HAS_TRI 0 HAS_OUT 1 HAS_IN 0 CAPTURE 0 BIT_CLEARING_EDGE_REGISTER 0 BIT_MODIFYING_OUTPUT_REGISTER 0 DATA_WIDTH 8 RESET_VALUE 0x0 EDGE_TYPE "NONE" IRQ_TYPE "NONE" FREQ 10000000u

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i2c_scl

altera_avalon_pio v10.1

Parameters bitClearingEdgeCapReg false bitModifyingOutReg false captureEdge false clockRate 50000000 direction Output edgeType RISING generateIRQ false irqType LEVEL resetValue 1 simDoTestBenchWiring false simDrivenValue 0 width 1 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments DO_TEST_BENCH_WIRING 0 DRIVEN_SIM_VALUE 0x0 HAS_TRI 0 HAS_OUT 1 HAS_IN 0 CAPTURE 0 BIT_CLEARING_EDGE_REGISTER 0 BIT_MODIFYING_OUTPUT_REGISTER 0 DATA_WIDTH 1 RESET_VALUE 0x1 EDGE_TYPE "NONE" IRQ_TYPE "NONE" FREQ 50000000u

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i2c_sda

altera_avalon_pio v10.1

Parameters bitClearingEdgeCapReg false bitModifyingOutReg false captureEdge false clockRate 50000000 direction Bidir edgeType RISING generateIRQ false irqType LEVEL resetValue 1 simDoTestBenchWiring false simDrivenValue 0 width 1 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments DO_TEST_BENCH_WIRING 0 DRIVEN_SIM_VALUE 0x0 HAS_TRI 1 HAS_OUT 0 HAS_IN 0 CAPTURE 0 BIT_CLEARING_EDGE_REGISTER 0 BIT_MODIFYING_OUTPUT_REGISTER 0 DATA_WIDTH 1 RESET_VALUE 0x1 EDGE_TYPE "NONE" IRQ_TYPE "NONE" FREQ 50000000u

---

sdram

altera_avalon_new_sdram_controller v10.1

Parameters TAC 5.5 TMRD 3 TRCD 20.0 TRFC 70.0 TRP 20.0 TWR 14.0 casLatency 3 clockRate 100000000 columnWidth 9 dataWidth 16 generateSimulationModel true initNOPDelay 0.0 initRefreshCommands 2 masteredTristateBridgeSlave model custom numberOfBanks 4 numberOfChipSelects 1 pinsSharedViaTriState false powerUpDelay 100.0 refreshPeriod 15.625 registerDataIn true rowWidth 13 size 33554432 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments REGISTER_DATA_IN 1 SIM_MODEL_BASE 1 SDRAM_DATA_WIDTH 16 SDRAM_ADDR_WIDTH 24 SDRAM_ROW_WIDTH 13 SDRAM_COL_WIDTH 9 SDRAM_NUM_CHIPSELECTS 1 SDRAM_NUM_BANKS 4 REFRESH_PERIOD 15.625 POWERUP_DELAY 100.0 CAS_LATENCY 3 T_RFC 70.0 T_RP 20.0 T_MRD 3 T_RCD 20.0 T_AC 5.5 T_WR 14.0 INIT_REFRESH_COMMANDS 2 INIT_NOP_DELAY 0.0 SHARED_DATA 0 STARVATION_INDICATOR 0 TRISTATE_BRIDGE_SLAVE "" IS_INITIALIZED 1 SDRAM_BANK_WIDTH 2 CONTENTS_INFO ""

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altpll_sys

altpll v10.1

Parameters HIDDEN_CUSTOM_ELABORATION altpll_avalon_elaboration HIDDEN_CUSTOM_POST_EDIT altpll_avalon_post_edit INTENDED_DEVICE_FAMILY Cyclone IV E WIDTH_CLOCK 5 WIDTH_PHASECOUNTERSELECT PRIMARY_CLOCK INCLK0_INPUT_FREQUENCY 20000 INCLK1_INPUT_FREQUENCY OPERATION_MODE NORMAL PLL_TYPE AUTO QUALIFY_CONF_DONE COMPENSATE_CLOCK CLK0 SCAN_CHAIN GATE_LOCK_SIGNAL GATE_LOCK_COUNTER LOCK_HIGH LOCK_LOW VALID_LOCK_MULTIPLIER INVALID_LOCK_MULTIPLIER SWITCH_OVER_ON_LOSSCLK SWITCH_OVER_ON_GATED_LOCK ENABLE_SWITCH_OVER_COUNTER SKIP_VCO SWITCH_OVER_COUNTER SWITCH_OVER_TYPE FEEDBACK_SOURCE BANDWIDTH BANDWIDTH_TYPE AUTO SPREAD_FREQUENCY DOWN_SPREAD SELF_RESET_ON_GATED_LOSS_LOCK SELF_RESET_ON_LOSS_LOCK CLK0_MULTIPLY_BY 2 CLK1_MULTIPLY_BY 2 CLK2_MULTIPLY_BY 1 CLK3_MULTIPLY_BY 4 CLK4_MULTIPLY_BY 1 CLK5_MULTIPLY_BY CLK6_MULTIPLY_BY CLK7_MULTIPLY_BY CLK8_MULTIPLY_BY CLK9_MULTIPLY_BY EXTCLK0_MULTIPLY_BY EXTCLK1_MULTIPLY_BY EXTCLK2_MULTIPLY_BY EXTCLK3_MULTIPLY_BY CLK0_DIVIDE_BY 1 CLK1_DIVIDE_BY 1 CLK2_DIVIDE_BY 5 CLK3_DIVIDE_BY 5 CLK4_DIVIDE_BY 25 CLK5_DIVIDE_BY CLK6_DIVIDE_BY CLK7_DIVIDE_BY CLK8_DIVIDE_BY CLK9_DIVIDE_BY EXTCLK0_DIVIDE_BY EXTCLK1_DIVIDE_BY EXTCLK2_DIVIDE_BY EXTCLK3_DIVIDE_BY CLK0_PHASE_SHIFT 0 CLK1_PHASE_SHIFT -1667 CLK2_PHASE_SHIFT 0 CLK3_PHASE_SHIFT 0 CLK4_PHASE_SHIFT 0 CLK5_PHASE_SHIFT CLK6_PHASE_SHIFT CLK7_PHASE_SHIFT CLK8_PHASE_SHIFT CLK9_PHASE_SHIFT EXTCLK0_PHASE_SHIFT EXTCLK1_PHASE_SHIFT EXTCLK2_PHASE_SHIFT EXTCLK3_PHASE_SHIFT CLK0_DUTY_CYCLE 50 CLK1_DUTY_CYCLE 50 CLK2_DUTY_CYCLE 50 CLK3_DUTY_CYCLE 50 CLK4_DUTY_CYCLE 50 CLK5_DUTY_CYCLE CLK6_DUTY_CYCLE CLK7_DUTY_CYCLE CLK8_DUTY_CYCLE CLK9_DUTY_CYCLE EXTCLK0_DUTY_CYCLE EXTCLK1_DUTY_CYCLE EXTCLK2_DUTY_CYCLE EXTCLK3_DUTY_CYCLE PORT_clkena0 PORT_UNUSED PORT_clkena1 PORT_UNUSED PORT_clkena2 PORT_UNUSED PORT_clkena3 PORT_UNUSED PORT_clkena4 PORT_UNUSED PORT_clkena5 PORT_UNUSED PORT_extclkena0 PORT_extclkena1 PORT_extclkena2 PORT_extclkena3 PORT_extclk0 PORT_UNUSED PORT_extclk1 PORT_UNUSED PORT_extclk2 PORT_UNUSED PORT_extclk3 PORT_UNUSED PORT_CLKBAD0 PORT_UNUSED PORT_CLKBAD1 PORT_UNUSED PORT_clk0 PORT_USED PORT_clk1 PORT_USED PORT_clk2 PORT_USED PORT_clk3 PORT_USED PORT_clk4 PORT_USED PORT_clk5 PORT_UNUSED PORT_clk6 PORT_clk7 PORT_clk8 PORT_clk9 PORT_SCANDATA PORT_UNUSED PORT_SCANDATAOUT PORT_UNUSED PORT_SCANDONE PORT_UNUSED PORT_SCLKOUT1 PORT_SCLKOUT0 PORT_ACTIVECLOCK PORT_UNUSED PORT_CLKLOSS PORT_UNUSED PORT_INCLK1 PORT_UNUSED PORT_INCLK0 PORT_USED PORT_FBIN PORT_UNUSED PORT_PLLENA PORT_UNUSED PORT_CLKSWITCH PORT_UNUSED PORT_ARESET PORT_USED PORT_PFDENA PORT_UNUSED PORT_SCANCLK PORT_UNUSED PORT_SCANACLR PORT_UNUSED PORT_SCANREAD PORT_UNUSED PORT_SCANWRITE PORT_UNUSED PORT_ENABLE0 PORT_ENABLE1 PORT_LOCKED PORT_USED PORT_CONFIGUPDATE PORT_UNUSED PORT_FBOUT PORT_PHASEDONE PORT_UNUSED PORT_PHASESTEP PORT_UNUSED PORT_PHASEUPDOWN PORT_UNUSED PORT_SCANCLKENA PORT_UNUSED PORT_PHASECOUNTERSELECT PORT_UNUSED PORT_VCOOVERRANGE PORT_VCOUNDERRANGE DPA_MULTIPLY_BY DPA_DIVIDE_BY DPA_DIVIDER VCO_MULTIPLY_BY VCO_DIVIDE_BY SCLKOUT0_PHASE_SHIFT SCLKOUT1_PHASE_SHIFT VCO_FREQUENCY_CONTROL VCO_PHASE_SHIFT_STEP USING_FBMIMICBIDIR_PORT SCAN_CHAIN_MIF_FILE AVALON_USE_SEPARATE_SYSCLK NO HIDDEN_CONSTANTS CT#CLK2_DIVIDE_BY 5 CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_USED CT#PORT_clk3 PORT_USED CT#PORT_clk2 PORT_USED CT#PORT_clk1 PORT_USED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 2 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#CLK3_DUTY_CYCLE 50 CT#CLK3_DIVIDE_BY 5 CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#CLK3_PHASE_SHIFT 0 CT#PORT_SCANCLKENA PORT_UNUSED CT#CLK4_DIVIDE_BY 25 CT#WIDTH_CLOCK 5 CT#PORT_SCANDATAOUT PORT_UNUSED CT#CLK4_MULTIPLY_BY 1 CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT 0 CT#CLK1_DUTY_CYCLE 50 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NORMAL CT#PORT_CONFIGUPDATE PORT_UNUSED CT#CLK1_MULTIPLY_BY 2 CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#CLK4_PHASE_SHIFT 0 CT#INCLK0_INPUT_FREQUENCY 20000 CT#CLK4_DUTY_CYCLE 50 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#CLK1_PHASE_SHIFT -1667 CT#PORT_ARESET PORT_USED CT#BANDWIDTH_TYPE AUTO CT#CLK2_MULTIPLY_BY 1 CT#INTENDED_DEVICE_FAMILY {Cyclone IV E} CT#PORT_SCANREAD PORT_UNUSED CT#CLK2_DUTY_CYCLE 50 CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_extclk3 PORT_UNUSED CT#PORT_extclk2 PORT_UNUSED CT#PORT_extclk1 PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_extclk0 PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK2_PHASE_SHIFT 0 CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 1 CT#CLK1_DIVIDE_BY 1 CT#CLK3_MULTIPLY_BY 4 CT#PORT_LOCKED PORT_USED HIDDEN_PRIVATES PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 50.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#OUTPUT_FREQ_UNIT4 MHz PT#OUTPUT_FREQ_UNIT3 MHz PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT2 MHz PT#OUTPUT_FREQ_UNIT1 MHz PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 1 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 1 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#USE_CLK4 1 PT#USE_CLK3 1 PT#USE_CLK2 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK1 1 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#LVDS_PHASE_SHIFT_UNIT4 deg PT#LVDS_PHASE_SHIFT_UNIT3 deg PT#PLL_AUTOPLL_CHECK 1 PT#OUTPUT_FREQ_MODE4 1 PT#LVDS_PHASE_SHIFT_UNIT2 deg PT#OUTPUT_FREQ_MODE3 1 PT#LVDS_PHASE_SHIFT_UNIT1 deg PT#OUTPUT_FREQ_MODE2 1 PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#OUTPUT_FREQ_MODE1 1 PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 1 PT#BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ4 2.00000000 PT#OUTPUT_FREQ3 40.00000000 PT#OUTPUT_FREQ2 10.00000000 PT#OUTPUT_FREQ1 100.00000000 PT#OUTPUT_FREQ0 100.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE 6 PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#PHASE_SHIFT4 0.00000000 PT#LOCKED_OUTPUT_CHECK 1 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT3 0.00000000 PT#DIV_FACTOR4 1 PT#PHASE_SHIFT2 0.00000000 PT#DIV_FACTOR3 1 PT#DIV_FACTOR2 1 PT#PHASE_SHIFT1 -60.00000000 PT#DIV_FACTOR1 1 PT#PHASE_SHIFT0 0.00000000 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 0 PT#USE_CLKENA4 0 PT#USE_CLKENA3 0 PT#USE_CLKENA2 0 PT#USE_CLKENA1 0 PT#USE_CLKENA0 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE4 2.000000 PT#EFF_OUTPUT_FREQ_VALUE3 40.000000 PT#EFF_OUTPUT_FREQ_VALUE2 10.000000 PT#EFF_OUTPUT_FREQ_VALUE1 100.000000 PT#EFF_OUTPUT_FREQ_VALUE0 100.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK4 1 PT#STICKY_CLK3 1 PT#STICKY_CLK2 1 PT#STICKY_CLK1 1 PT#STICKY_CLK0 1 PT#MIRROR_CLK4 0 PT#EXT_FEEDBACK_RADIO 0 PT#MIRROR_CLK3 0 PT#MIRROR_CLK2 0 PT#MIRROR_CLK1 0 PT#MIRROR_CLK0 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#CLKLOSS_CHECK 0 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#PHASE_SHIFT_UNIT4 deg PT#PHASE_SHIFT_UNIT3 deg PT#PHASE_SHIFT_UNIT2 deg PT#PHASE_SHIFT_UNIT1 deg PT#PHASE_SHIFT_UNIT0 deg PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR4 1 PT#MULT_FACTOR3 1 PT#MULT_FACTOR2 1 PT#MULT_FACTOR1 1 PT#MULT_FACTOR0 1 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#DUTY_CYCLE4 50.00000000 PT#DUTY_CYCLE3 50.00000000 PT#DUTY_CYCLE2 50.00000000 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE1 50.00000000 PT#INTENDED_DEVICE_FAMILY {Cyclone IV E} PT#DUTY_CYCLE0 50.00000000 PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1290674183995785.mif PT#ACTIVECLK_CHECK 0 HIDDEN_USED_PORTS UP#locked used UP#c4 used UP#c3 used UP#c2 used UP#c1 used UP#c0 used UP#areset used UP#inclk0 used HIDDEN_IS_NUMERIC IN#WIDTH_CLOCK 1 IN#CLK0_DUTY_CYCLE 1 IN#CLK2_DIVIDE_BY 1 IN#PLL_TARGET_HARCOPY_CHECK 1 IN#CLK3_DIVIDE_BY 1 IN#CLK4_MULTIPLY_BY 1 IN#CLK1_MULTIPLY_BY 1 IN#CLK3_DUTY_CYCLE 1 IN#CLK4_DIVIDE_BY 1 IN#SWITCHOVER_COUNT_EDIT 1 IN#INCLK0_INPUT_FREQUENCY 1 IN#PLL_LVDS_PLL_CHECK 1 IN#PLL_AUTOPLL_CHECK 1 IN#PLL_FASTPLL_CHECK 1 IN#CLK1_DUTY_CYCLE 1 IN#PLL_ENHPLL_CHECK 1 IN#CLK2_MULTIPLY_BY 1 IN#DIV_FACTOR4 1 IN#DIV_FACTOR3 1 IN#DIV_FACTOR2 1 IN#DIV_FACTOR1 1 IN#DIV_FACTOR0 1 IN#LVDS_MODE_DATA_RATE_DIRTY 1 IN#CLK4_DUTY_CYCLE 1 IN#CLK2_DUTY_CYCLE 1 IN#GLOCK_COUNTER_EDIT 1 IN#CLK0_DIVIDE_BY 1 IN#CLK3_MULTIPLY_BY 1 IN#MULT_FACTOR4 1 IN#MULT_FACTOR3 1 IN#MULT_FACTOR2 1 IN#MULT_FACTOR1 1 IN#MULT_FACTOR0 1 IN#CLK0_MULTIPLY_BY 1 IN#USE_MIL_SPEED_GRADE 1 IN#CLK1_DIVIDE_BY 1 HIDDEN_MF_PORTS MF#areset 1 MF#clk 1 MF#locked 1 MF#inclk 1 HIDDEN_IF_PORTS IF#locked {output 0} IF#reset {input 0} IF#clk {input 0} IF#readdata {output 32} IF#write {input 0} IF#phasedone {output 0} IF#c4 {output 0} IF#c3 {output 0} IF#c2 {output 0} IF#address {input 2} IF#c1 {output 0} IF#c0 {output 0} IF#writedata {input 32} IF#read {input 0} HIDDEN_IS_FIRST_EDIT 0 AUTO_INCLK_INTERFACE_CLOCK_RATE 50000000 AUTO_DEVICE_FAMILY Cyclone IV E deviceFamily Cyclone IV E generateLegacySim false

  

Software Assignments (none)

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clock_crossing_io

altera_avalon_clock_crossing v10.1

Parameters dataWidth 32 downstreamFIFODepth 16 downstreamUseRegister false masterSyncDepth 3 maxBurstSize 8 slaveAddressWidth 5 slaveSyncDepth 3 upstreamFIFODepth 32 upstreamUseRegister false useBurstCount false deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

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g_sensor_int

altera_avalon_pio v10.1

Parameters bitClearingEdgeCapReg false bitModifyingOutReg false captureEdge true clockRate 10000000 direction Input edgeType RISING generateIRQ true irqType EDGE resetValue 0 simDoTestBenchWiring false simDrivenValue 0 width 1 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments DO_TEST_BENCH_WIRING 0 DRIVEN_SIM_VALUE 0x0 HAS_TRI 0 HAS_OUT 0 HAS_IN 1 CAPTURE 1 BIT_CLEARING_EDGE_REGISTER 0 BIT_MODIFYING_OUTPUT_REGISTER 0 DATA_WIDTH 1 RESET_VALUE 0x0 EDGE_TYPE "RISING" IRQ_TYPE "EDGE" FREQ 10000000u

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epcs

altera_avalon_epcs_flash_controller v10.1

Parameters autoSelectASMIAtom true deviceFamilyString Cyclone IV E useASMIAtom false deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments REGISTER_OFFSET 1024

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clock_crossing_io2

altera_avalon_clock_crossing v10.1

Parameters dataWidth 32 downstreamFIFODepth 16 downstreamUseRegister false masterSyncDepth 3 maxBurstSize 8 slaveAddressWidth 10 slaveSyncDepth 3 upstreamFIFODepth 64 upstreamUseRegister false useBurstCount false deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

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jtag_uart

altera_avalon_jtag_uart v10.1

Parameters allowMultipleConnections false hubInstanceID 0 readBufferDepth 64 readIRQThreshold 8 simInputCharacterStream simInteractiveOptions INTERACTIVE_ASCII_OUTPUT useRegistersForReadBuffer false useRegistersForWriteBuffer false useRelativePathForSimFile false writeBufferDepth 64 writeIRQThreshold 8 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments WRITE_DEPTH 64 READ_DEPTH 64 WRITE_THRESHOLD 8 READ_THRESHOLD 8

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adc_spi_read

TERASIC_ADC_READ v1.0

Parameters AUTO_CLOCK_CLOCK_RATE 2000000 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

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gsensor_spi

TERASIC_SPI_3WIRE v1.0

Parameters AUTO_CLOCK_RESET_CLOCK_RATE 50000000 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

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select_i2c_clk

altera_avalon_pio v10.1

Parameters bitClearingEdgeCapReg false bitModifyingOutReg false captureEdge false clockRate 10000000 direction Output edgeType RISING generateIRQ false irqType LEVEL resetValue 0 simDoTestBenchWiring false simDrivenValue 0 width 1 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments DO_TEST_BENCH_WIRING 0 DRIVEN_SIM_VALUE 0x0 HAS_TRI 0 HAS_OUT 1 HAS_IN 0 CAPTURE 0 BIT_CLEARING_EDGE_REGISTER 0 BIT_MODIFYING_OUTPUT_REGISTER 0 DATA_WIDTH 1 RESET_VALUE 0x0 EDGE_TYPE "NONE" IRQ_TYPE "NONE" FREQ 10000000u