R. G. Herb Condensed Matter Seminars |
Events on Tuesday, March 5th, 2013
- Analysis of high-fidelity gate design and error thresholds for fault-tolerant superconducting quantum computing architectures
- Time: 10:00 am
- Place: 5280 Chamberlin Hall
- Speaker: Joydip Ghosh, University of Georgia
- Abstract: Quantum computing with superconducting elements promises scalability and is widely regarded as a viable approach to develop a fault-tolerant architecture of a candidate quantum computer. In this talk, I first discuss our recent proposal to design high-fidelity controlled-σz (CZ) operations using only DC bias control and then explore the performance of various existing superconducting surface code based architectures under a realistic multi-parameter error model. Assuming phase or transmon qubits and using only low frequency qubit-bias control, our CZ operation exhibits threshold fidelity (intrinsic) with a realistic two-parameter pulse profile. In addition we have an analytic model that estimates the fidelities of CZ gates as a function of various pulse parameters as well as quantifies the error due to any perturbation over an optimal pulse shape. Next we consider a realistic, multi-parameter error model and investigate the performance of the surface code for three possible fault-tolerant superconducting architectures. We map amplitude and phase damping to an asymmetric depolarization channel via the Pauli twirl approximation, and obtain the logical error rate as a function of the qubit coherence time, intrinsic state preparation and gate and readout errors. A numerical Monte Carlo simulation is performed to obtain the logical error rates and a leading order analytic model is constructed to estimate their scaling behavior below threshold. Our results suggest that large-scale fault-tolerant quantum computation should be possible with existing superconducting devices.
- Host: Friesen & Coppersmith